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1 typical application description 8-channel, 10v input 12-/14-/16-bit, 100ksps adc converters with shutdown the ltc ? 1854/ltc1855/ltc1856 are 8-channel, low power, 12-/14-/16-bit, 100ksps, analog-to-digital con - verters (adcs). these adcs operate from a single 5v supply and the 8- channel multiplexer can be programmed for single-ended inputs, pairs of differential inputs, or combinations of both. in addition, all channels are fault protected to 30v. a fault condition on any channel will not affect the conversion result of the selected channel. an onboard precision reference minimizes external com - ponents. power dissipation is 40mw at 100ksps and lower in two power shutdown modes (27.5mw in nap mode and 40w in sleep mode.) dc specifcations include 3lsb inl for the ltc1856, 1.5lsb inl for the ltc1855 and 1lsb for the ltc1854. the internal clock is trimmed for 5s maximum conversion time and the sampling rate is guaranteed at 100ksps. a separate convert start input and data ready signal (busy) ease connections to fifos, dsps and microprocessors. 100khz, 12-bit/14-/16-bit sampling adc l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. features applications n single 5v supply n sample rate: 100ksps n 8-channel multiplexer with 30v protection n 10v bipolar input range single ended or differential n 3lsb inl for the ltc1856, 1.5lsb inl for the ltc1855, 1lsb inl for the ltc1854 n power dissipation: 40mw (typ) n spi/microwire? compatible serial i/o n power shutdown: nap and sleep n sinad: 87db (ltc1856) n operates with internal or external reference n internal synchronized clock n 28-pin ssop package n industrial process control n multiplexed data acquisition systems n high speed data acquisition for pcs n digital signal processing ltc1856 typical inl curve com ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 muxout + muxout ? adc + adc ? agnd1 convst rd sck sdi dgnd sdo busy ov dd dv dd av dd agnd3 agnd2 refcomp v ref ltc1854/ ltc1855/ ltc1856 software-programmable single-ended or differential inputs 10v bipolar input range 10f 0.1 f 10f 10f 0.1 f 1 f 10f 3v to 5v 5v 5v 2.5v 0.1 f p control lines 0.1 f code ?32768 inl (lsb) 0 0.5 1.0 0 185456 g01 ?0.5 ?1.0 ?2.0 ?16384 16384 32767 ?1.5 2.0 1.5 ltc1854/ltc1855/ltc1856 1854565af
2 package/order information absolute maximum ratings supply voltage (ov dd = dv dd = av dd = v dd ) ............ 6v ground voltage difference dgnd, agnd1, agnd2, agnd3 ....................... 0.3v analog input voltage adc + , adc C (note 3) ................... (agnd1 C 0.3v) to (av dd + 0.3v) ch0-ch7, com ................................................... 30v digital input voltage (note 4) ...... (dgnd C 0.3v) to 10v digital output voltage .... (dgnd C 0.3v) to (dv dd + 0.3v) power dissipation ................................................ 500mw operating temperature range ltc1854c/ltc1855c/ltc1856c .............. 0c to 70c ltc1854i/ltc1855i/ltc1856i ............. C 40c to 85c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) .................. 300c (notes 1, 2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view g package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 com ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 muxout + muxout ? adc + adc ? agnd1 convst rd sck sdi dgnd sdo busy ov dd dv dd av dd agnd3 agnd2 refcomp v ref t jmax = 125c, ja = 160c/w exposed pad (pin #) is gnd, must be soldered to pcb order part number ltc1854cg ltc1854ig ltc1855cg ltc1855ig ltc1856cg ltc1856ig order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts specifed with wider operating temperature ranges. parameter conditions ltc1854 ltc1855 ltc1856 units min typ max min typ max min typ max resolution l 12 14 15 bits no missing codes l 12 14 15 bits transition noise 0.06 0.25 1 lsb rms integral linearity error (note 7) l 1 1.5 3 lsb differential linearity error l C1 1 C1 1.5 C2 4 lsb bipolar zero error (note 8) l 5 8 23 lsb bipolar zero error drift 0.1 0.1 0.1 ppm/c bipolar zero error match 3 4 10 lsb bipolar full-scale error external reference (note 11) internal reference (note 11) l 0.34 0.45 0.14 0.40 0.1 0.4 % % bipolar full-scale error drift external reference internal reference 2.5 7 2.5 7 2.5 7 ppm/c ppm/c bipolar full-scale error match 5 10 15 lsb input common mode range l 10 +10 10 v input common mode rejection ratio 96 96 96 db converter and multiplexer characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. muxout connected to adc inputs. (notes 5, 6) ltc1854/ltc1855/ltc1856 185456fa
3 analog input the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 5) parameter conditions min typ max units analog input range ch0 to ch7, com 10 v adc + , adc C (note 3) adc C 2.048 v impedance ch0 to ch7, com 31 k muxout + , muxout C 5 k capacitance ch0 to ch7, com 5 pf sample mode adc + , adc C 12 pf hold mode adc + , adc C 4 pf input leakage current adc + , adc C , convst = low l 1 a dynamic accuracy the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. muxout connected to adc inputs. (note 5) symbol parameter conditions ltc1854 ltc1855 ltc1856 units min typ max min typ max min typ max s/(n + d) signal-to-(noise + distortion) ratio 1khz input signal 74 83 87 db thd total harmonic distortion 1khz input signal first five harmonics C102 C95 C101 db peak harmonic or spurious noise 1khz input signal C99 C99 C103 db channel-to-channel isolation 1khz input signal C120 C120 C120 db C3db input bandwidth 1 1 1 mhz aperture delay C70 C70 C70 ns aperture jitter 60 60 60 ps transient response full-scale step (note 9) 4 4 4 s overvoltage recovery (note 12) 150 150 150 ns ltc1854/ltc1855/ltc1856 1854565af
4 internal reference characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 5) parameter conditions min typ max units v ref output voltage i out = 0 l 2.475 2.50 2.525 v v ref output temperature coeffcient i out = 0 10 ppm/c v ref output impedance C0.1ma i out 0.1ma 8 k v refcomp output voltage i out = 0 4.096 v symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in digital input current v in = 0v to v dd l 10 a c in digital input capacitance 5 pf v oh high level output voltage v dd = 4.75v, i o = C10a, ov dd = v dd v dd = 4.75v, i o = C200a, ov dd = v dd l 4 4.74 v v v ol low level output voltage v dd = 4.75v, i o = 160a, ov dd = v dd v dd = 4.75v, i o = 1.6ma, ov dd = v dd l 0.05 0.10 0.4 v v i oz hi-z output leakage v out = 0v to v dd , rd = high l 10 a c oz hi-z output capacitance rd = high 15 pf i source output source current v out = 0v C10 ma i sink output sink current v out = v dd 10 ma digital inputs and digital outputs the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 5) power requirements the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 5) parameter conditions min typ max units positive supply voltage (notes 9 and 10) 4.75 5.00 5.25 v positive supply current nap mode sleep mode convst = 0v or 5v l 8.0 5.5 8.0 12 7 13 ma ma a power dissipation nap mode sleep mode convst = 0v or 5v 40.0 27.5 40.0 mw mw w ltc1854/ltc1855/ltc1856 185456fa
5 timing characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with dgnd, agnd1, agnd2 and agnd3 wired together unless otherwise noted. note 3: when these pin voltages are taken below ground or above av dd = dv dd = ov dd = v dd , they will be clamped by internal diodes. this product can handle currents of greater than 100ma below ground or above v dd without latchup. note 4: when these pin voltages are taken below ground they will be clamped by internal diodes. this product can handle currents of greater than 100ma below ground without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, f sample = 100khz, t r = t f = 5ns unless otherwise specifed. note 6: linearity, offset and full-scale specifcations apply for a single- ended analog mux input with respect to ground or adc + with respect to adc C tied to ground. symbol parameter conditions min typ max units f sample(max) maximum sampling frequency through ch0 to ch7 inputs through adc + , adc C only l 100 166 khz khz t conv conversion time l 4 5 s t acq acquisition time through ch0 to ch7 inputs through adc + , adc C only l 1 4 s s f sck sck frequency (note 13) l 0 20 mhz t r sdo rise time see test circuits 6 ns t f sdo fall time see test circuits 6 ns t 1 convst high time l 40 ns t 2 convst to busy delay c l = 25pf, see test circuits l 15 30 ns t 3 sck period l 50 ns t 4 sck high l 10 ns t 5 sck low l 10 ns t 6 delay time, sck to sdo valid c l = 25pf, see test circuits l 25 45 ns t 7 time from previous sdo data remains valid after sck c l = 25pf, see test circuits l 5 20 ns t 8 sdo valid after rd c l = 25pf, see test circuits l 11 30 ns t 9 rd to sck setup time l 20 ns t 10 sdi setup time before sck l 0 ns t 11 sdi hold time after sck l 7 ns t 12 sdo valid before busy rd = low, c l = 25pf, see test circuits l 5 20 ns t 13 bus relinquish time see test circuits l 10 30 ns the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 5) note 7: integral nonlinearity is defned as the deviation of a code from a straight line passing through the actual end points of the transfer curve. the deviation is measured from the center of the quantization band. note 8: bipolar zero error is the offset voltage measured from C 0.5lsb when the output code fickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 for the ltc1856, between 00 0000 0000 0000 and 11 1111 1111 1111 for the ltc1855 and between 0000 0000 0000 and 1111 1111 1111 for the ltc1854. note 9: guaranteed by design, not subject to test. note 10: recommended operating conditions. note 11: full-scale bipolar error is the worst case of Cfs or +fs untrimmed deviation from ideal frst and last code transitions, divided by the full-scale range, and includes the effect of offset error. note 12: recovers to specifed performance after (2 ? fs) input overvoltage. note 13: t 6 of 45ns maximum allows f sck up to 10mhz for rising capture with 50% duty cycle and f sck up to 20mhz for falling capture (with 5ns setup time for the receiving logic). ltc1854/ltc1855/ltc1856 1854565af
6 typical performance characteristics ltc1855 typical inl curve ltc1855 typical dnl curve ltc1855 nonaveraged 4096-point fft plot ltc1854 typical inl curve ltc1854 typical dnl curve ltc1854 nonaveraged 4096-point fft plot ltc1856 typical inl curve ltc1856 typical dnl curve ltc1856 nonaveraged 4096-point fft plot code ?32768 inl (lsb) 0 0.5 1.0 32767 185456 g01 ?0.5 ?1.0 ?2.0 ?16384 0 16384 ?1.5 2.0 1.5 code ?32768 dnl (lsb) 0 0.5 1.0 32767 185456 g02 ?0.5 ?1.0 ?2.0 ?16384 0 16384 ?1.5 2.0 1.5 frequency (khz) 0 15 25 50 185456 g03 5 10 20 30 40 45 35 magnitude (db) ?60 ?40 ?20 0 ?80 ?100 ?70 ?50 ?30 ?10 ?90 ?110 ?130 ?120 f sample = 100khz f in = 1khz sinad = 87db thd = ?101db code ?8192 inl (lsb) 0 0.4 0.2 0.6 8191 185455 g04 ?0.2 ?0.6 ?0.4 ?1 ?4096 0 4096 ?0.8 1 0.8 code ?8192 dnl (lsb) 0 0.4 0.2 0.6 8191 185456 g05 ?0.2 ?0.4 ?1 ?4096 0 4096 ?0.6 ?0.8 1 0.8 frequency (khz) 0 15 25 50 185456 g06 5 10 20 30 40 45 35 magnitude (db) ?60 ?40 ?20 0 ?80 ?100 ?70 ?50 ?30 ?10 ?90 ?110 ?130 ?120 f sample = 100khz f in = 1khz sinad = 83db thd = ?95db code ?2048 ?1.0 inl (lsb) ?0.8 ?0.4 ?0.2 0 1.0 0.4 ?1024 0 185456 g07 ?0.6 0.6 0.8 0.2 1024 2047 code ?2048 ?1.0 dnl (lsb) ?0.8 ?0.4 ?0.2 0 1.0 0.4 ?1024 0 185456 g08 ?0.6 0.6 0.8 0.2 1024 2047 frequency (khz) 0 magnitude (db) ?70 ?30 0 40 185456 g09 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 10 20 30 50 f sample = 100khz f in = 1khz sinad = 73.6db thd = ?102db ltc1854/ltc1855/ltc1856 185456fa
7 typical performance characteristics ltc1855 sinad vs input frequency ltc1855 total harmonic distortion vs input frequency ltc1855 channel-to-channel offset error matching vs temperature ltc1854 sinad vs input frequency ltc1854 total harmonic distortion vs input frequency ltc1854 channel-to-channel offset error matching vs temperature ltc1856 sinad vs input frequency ltc1856 total harmonic distortion vs input frequency ltc1856 channel-to-channel offset error matching vs temperature input frequency (khz) 1 74 sinad (db) 78 82 90 10 100 185456 g10 86 76 80 88 84 input frequency (khz) 1 ?110 total harmonic distortion (db) ?100 ?90 ?70 10 100 185456 g11 ?80 temperature (c) ?50 ?1.0 channel-to-channel offset error matching (lsbs) ?0.5 0 0.5 1.0 ?25 0 25 50 185456 g12 75 100 input frequency (khz) 1 60 sinad (db) 85 10 100 185456 g13 65 70 80 75 input frequency (khz) 1 ?110 total harmonic distortion (db) ?100 ?90 ?60 10 100 185456 g14 ?80 ?70 temperature (c) ?50 ?0.5 channel-to-channel offset error matching (lsbs) ?0.25 0 0.25 0.5 ?25 0 25 50 185456 g15 75 100 input frequency (khz) 1 60 sinad (db) 65 70 80 10 100 185456 g16 75 input frequency (khz) total harmonic distortion (db) ?60 ?70 ?80 185456 g17 ?110 ?90 ?100 100 1 10 temperature (c) ?50 ?0.25 channel-to-channel offset error matching (lsb) ?0.15 ?0.05 0.05 ?25 0 25 50 185456 g18 75 0.15 0.25 ?0.20 ?0.10 0 0.10 0.20 100 ltc1854/ltc1855/ltc1856 1854565af
8 typical performance characteristics internal reference voltage vs temperature change in refcomp voltage vs load current ltc1856 power supply feedthrough vs ripple frequency supply current vs supply voltage supply current vs temperature ltc1856 channel-to-channel gain error matching vs temperature ltc1855 channel-to-channel gain error matching vs temperature ltc1854 channel-to-channel gain error matching vs temperature temperature (c) ?50 ?1.0 channel-to-channel gain error matching (lsbs) ?0.5 0 0.5 1.0 ?25 0 25 50 185456 g19 75 100 temperature (c) ?50 ?0.5 channel-to-channel gain error matching (lsbs) ?0.25 0 0.25 0.5 ?25 0 25 50 185456 g20 75 100 temperature (c) ?50 ?0.25 channel-to-channel gain error matching (lsb) ?0.15 ?0.05 0.05 ?25 0 25 50 185456 g21 75 0.15 0.25 ?0.20 ?0.10 0 0.10 0.20 100 temperature (c) ?50 internal reference voltage (v) 25 75 185456 g22 ?25 0 50 2.520 2.515 2.510 2.505 2.500 2.495 2.490 2.485 2.480 100 load current (ma) ?50 ?0.04 change in refcomp voltage (v) ?0.02 0 0.02 0.04 ?40 ?30 ?20 ?10 185456 g23 0 10 ripple frequency (hz) ?60 power supply feedthrough (db) ?40 ?20 ?10 100 10k 100k 1m 185456 g24 ?80 1k ?30 ?50 ?70 f sample = 100khz v ripple = 60mv supply voltage (v) 4.5 supply current (ma) 8.0 8.5 5.5 185454 g25 7.5 7.0 4.75 5 5.25 9.0 f sample = 100khz temperature (c) ?50 7.0 positive supply current (ma) 7.5 8.0 8.5 9.0 ?25 0 25 50 185456 g26 75 100 f sample = 100khz ltc1854/ltc1855/ltc1856 185456fa
9 pin functions com (pin 1): common input. this is the negative reference point for all single-ended inputs. it must be free of noise and is usually connected to the analog ground plane. ch0 (pin 2): analog mux input. ch1 (pin 3): analog mux input. ch2 (pin 4): analog mux input. ch3 (pin 5): analog mux input. ch4 (pin 6): analog mux input. ch5 (pin 7): analog mux input. ch6 (pin 8): analog mux input. ch7 (pin 9): analog mux input. muxout + (pin 10): positive mux output. output of the analog multiplexer. connect to adc + for normal opera - tion. muxout C (pin 11): negative mux output. output of the analog multiplexer. connect to adc C for normal opera - tion. adc + (pin 12): positive analog input to the analog-to- digital converter. adc C (pin 13): negative analog input to the analog-to- digital converter. agnd1 (pin 14): analog ground. v ref (pin 15): 2.5v reference output. bypass to analog ground with a 1f tantalum capacitor. refcomp (pin 16): reference buffer output. bypass to analog ground with a 10f tantalum and a 0.1f ceramic capacitor. nominal output voltage is 4.096v. agnd2 (pin 17): analog ground. agnd3 (pin 18): analog ground. this is the substrate connection. av dd (pin 19): 5v analog supply. bypass to analog ground with a 0.1f ceramic and a 10f tantalum capacitor. dv dd (pin 20): 5v digital supply. bypass to digital ground with a 0.1f ceramic and a 10f tantalum capacitor. ov dd (pin 21): positive supply for the digital output buffers (3v to 5v). bypass to digital ground with a 0.1f ceramic and a 10f tantalum capacitor. busy (pin 22): output shows converter status. it is low when a conversion is in progress. sdo (pin 23): serial data output. ltc1854/ltc1855/ltc1856 1854565af
10 functional block diagram pin functions dgnd (pin 24): digital ground. sdi (pin 25): serial data input. sck (pin 26): serial data clock. rd (pin 27): read input. this active low signal enables the digital output pin sdo and enables the serial interface, sdi and sck are ignored when rd is high. convst (pin 28): conversion start. the adc starts a conversion on convsts rising edge. 2.5v reference internal clock 1.6384x 4.096v 8k agnd1 control logic serial i/o input mux agnd3 agnd2 refcomp v ref adc ? muxout + muxout ? adc + dgnd av dd dv dd mux address data out convst 19 20 28 25 2 3 9 1 22 26 27 21 23 24 18 17 16 15 13 12 10 11 14 sdi busy sck rd ov dd sdo 18545 bd 12-/14-/16-bit sampling adc + ? com ch7 ch1 ? ? ? ch0 ltc1854/ltc1855/ltc1856 185456fa
11 test circuits timing diagrams load circuits for access timing load circuits for output float delay 1k (a) hi-z to v oh and v ol to v oh 25pf 1k 5v dn dn (b) hi-z to v ol and v oh to v ol 25pf 18545 tc01 1k (a) v oh to hi-z 25pf 1k 5v dn dn (b) v ol to hi-z 25pf 18545 tc02 t 1 (for short pulse mode) t 1 convst 50% 18545 td01 50% t 2 (convst to busy delay) t 2 convst busy 2.4v 0.4v 18545 td02 t 3 , t 4 , t 5 (sck timing) sck 18545 td03 t 4 t 5 t 3 t 6 (delay time, sck to sdo valid) t 7 (time from previous data remains valid after sck) t 6 t 7 sck sdo 2.4v 0.4v 0.4v 18545 td04 t 8 (sdo valid after rd ) t 8 rd sdo 2.4v 0.4v 0.4v 18545 td05 hi-z t 9 (rd to sck setup time) t 9 0.4v 2.4v 18545 td06 rd sck ltc1854/ltc1855/ltc1856 1854565af
12 timing diagrams t 10 (sdi setup time before sck) t 10 sck sdi 2.4v 2.4v 0.4v 18545 td07 t 11 (sdi hold time after sck) t 11 sck sdi 2.4v 2.4v 0.4v 18545 td08 t 12 (sdo valid before busy , rd = 0) t 12 busy sdo 2.4v b15 2.4v 18545 td09 t 13 (bus relinquish time) t 13 rd sdo 2.4v 18545 td10 10% 90% hi-z ltc1854/ltc1855/ltc1856 185456fa
13 applications information o verview the ltc1854/ltc1855/ltc1856 are innovative, multi- channel adcs. the on-chip resistors provide attenuation and offset for each channel. the precisely trimmed attenua - tors ensure an accurate input range. because they precede the multiplexer, errors due to multiplexer on-resistance are eliminated. the input word selects the single ended or differential inputs for each channel or pair of channels. overrange protection is provided for unselected channels. an over - range condition on an unused channel will not affect the conversion result on the selected channel. conversion d etails the ltc1854/ltc1855/ltc1856 use a successive ap - proximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-/14-/16-bit serial output respectively. the adcs are complete with a precision reference and an internal clock. the control logic provides easy interface to microprocessors and dsps. (please refer to the digital interface section for the data format.) the analog signals applied at the mux input channels are rescaled by the resistor divider network formed by r1, r2 and r3 as shown below. the rescaled signals appear on the muxout (pins 10, 11) which are also connected to the adc inputs (pins 12, 13) under normal operation. before starting a conversion, an 8-bit data word is clocked into the sdi input on the frst eight rising sck edges to select the mux address and power down mode. the adc enters acquisition mode on the falling edge of the sixth clock in the 8-bit data word and ends on the rising edge of the convst signal which also starts a conversion (see figure 7). a minimum time of 4s will provide enough time for the sample-and-hold capacitors to acquire the analog signal. once a conversion cycle has begun, it cannot be restarted. during the conversion, the internal differential 12-/14-/16- bit capacitive dac output is sequenced by the sar from the most signifcant bit (msb) to the least signifcant bit (lsb). the input is successively compared with the binary weighted charges supplied by the differential capacitive dac. bit decisions are made by a high speed comparator. at the end of a conversion, the dac output balances the analog input (adc + C adc C ). the sar contents (a 12-/14-/16-bit data word) which represents the difference of adc + and adc C are loaded into the 12-/14-/16-bit shift register. driving the analog inputs the input range for the ltc1854/ltc1855/ltc1856 is 10v and the mux inputs are overvoltage protected to 30v. the input impedance is typically 31k; therefore, it should be driven with a low impedance source. wideband noise coupling into the input can be minimized by placing a 3000pf capacitor at the input as shown in figure 2. an npo-type capacitor gives the lowest distortion. place the capacitor as close to the device input pin as possible. if an amplifer is to be used to drive the input, care should be taken to select an amplifer with adequate accuracy, linearity and noise for the application. the following list is a summary of the op amps that are suitable for driving the ltc1854/ltc1855/ltc1856. more detailed information is available in the linear technology data books and online at www.linear.com. lt ? 1007: low noise precision amplifer. 2.7ma supply current 5v to 15v supplies. gain bandwidth product 8mhz. dc applications. mux input r1 25k refcomp ch sel r3 10k 185456 ai01 r2 17k muxout ltc1854/ltc1855/ltc1856 1854565af
14 applications information lt1227: 140mhz video current feedback amplifer. 10ma supply current. 5v to 15v supplies. low noise and low distortion. lt1468/lt1469: single and dual 90mhz, 16-bit accurate op amp. good ac/dc specs. 5v to 15v supplies. lt1677: single, low noise op amp. rail-to-rail input and output. up to 15v supplies. lt1792: single, low noise jfet input op amp, 5v sup - plies. lt1793: single, low noise jfet input op amp, 10pa bias current, 5v supplies. lt1881/lt1882: dual and quad, 200pa bias current, rail- to-rail output op amps. up to 15v supplies. lt1844/lt1885: dual and quad, 400pa bias current, rail-to-rail output op amps. up to 15v supplies. faster response and settling time. internal v oltage reference the ltc1854/ltc1855/ltc1856 have an on-chip, tem - perature compensated, curvature corrected, bandgap reference, which is factory trimmed to 2.50v. the full-scale range of the ltc1854/ltc1855/ltc1856 is equal to 10v. the output of the reference is connected to the input of a gain of 1.6384x buffer through an 8k resistor (see figure 3). the input to the buffer or the output of the reference figure 2. analog input filtering figure 1. ltc1854/ltc1855/ltc1856 simplifed equivalent circuit 2.5v reference internal clock 1.6384x 4.096v 8k agnd1 control logic serial i/o input mux agnd3 agnd2 refcomp v ref adc ? muxout + muxout ? adc + dgnd av dd dv dd mux address data out convst sdi busy sck rd ov dd sdo 18545 f01 12-/14-/16-bit sampling adc + ? com ch7 ch1 ? ? ? ch0 3000pf 18545 f02 a in + a in ? ch0 ch1 muxout + muxout ? adc + adc ? ? ? ? ? ltc1854/ltc1855/ltc1856 185456fa
15 applications information is available at v ref (pin 15). the internal reference can be overdriven with an external reference if more accuracy is needed. the buffer output drives the internal dac and is available at refcomp (pin 16). the refcomp pin can be used to drive a steady dc load of less than 2ma. driving an ac load is not recommended because it can cause the performance of the converter to degrade. for minimum code transition noise the v ref pin and the refcomp pin should each be decoupled with a capacitor to flter wideband noise from the reference and the buffer. full scale and offset figure 4 shows the ideal input/output characteristics for the ltc1856. the code transitions occur midway be - tween successive integer lsb values (i.e., Cfs+0.5lsb, Cfs+1.5lsb, Cfs+2.5lsb, fsC1.5lsb, fsC0.5lsb). the output is twos complement binary with: 1 ls b = f s ? ( ? f s ) 65566 = 20v 65536 = 305.2 v in applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero during a calibration sequence. offset error must be adjusted before full-scale error. zero offset is achieved by adjusting the offset applied to the C input. for single-ended inputs, this offset should be applied to the com pin. for differential inputs, the C input is dictated by the mux address. for zero offset error, apply C 0.5lsb to the + input and adjust the offset at the C input until the output code fick - ers between 0000 0000 0000 0000 and 1111 1111 1111 1111 for the ltc1856, between 00 0000 0000 0000 and 11 1111 1111 1111 for the ltc1855 and between 0000 0000 0000 and 1111 1111 1111 for the ltc1854. for full-scale adjustment, an input voltage of fs C 1.5lsbs should be applied to the + input and the appropriate reference adjusted until the output code fickers between 0111 1111 1111 1110 and 0111 1111 1111 1111 for the ltc1856, between 01 1111 1111 1110 and 01 1111 1111 1111 for the ltc1855 and between 0111 1111 1110 and 0111 1111 1111 for the ltc1854. these adjustments as well as the factory trims affect all channels. the channel-to-channel offset and gain error matching are guaranteed by design to meet the specifca - tions in the converter characteristics table. figure 3. internal or external reference source figure 4. bipolar transfer characteristics 2.5v reference 18545 f03 12-/14-/16-bit capacitive dac 1.6384x buffer 8k v ref 1f 15 2.5v 16 refcomp 0.1f 4.096v 10f 185456 f04 011...111 011...110 000...001 000...000 111...111 111...110 100...001 100...000 fs ? 1lsb ?(fs ? 1lsb) input voltage (v) output code ltc1854/ltc1855/ltc1856 1854565af
16 applications information dc performance one way of measuring the transition noise associated with a high resolution adc is to use a technique where a dc signal is applied to the input of the mux and the resulting output codes are collected over a large number of conversions. for example in figure 5 the distribution of output code is shown for a dc input that has been digitized 4096 times. the distribution is gaussian and the rms code transition is about 1lsb for the ltc1856. d igital i nterface internal clock the adc has an internal clock that is trimmed to achieve a typical conversion time of 4s. no external adjustments are required and, with the maximum acquisition time of 4s, throughput performance of 100ksps is assured. 3v input/output compatible the ltc1854/ltc1855/ltc1856 operate on a 5v supply, which makes the devices easy to interface to 5v digital systems. these devices can also interface to 3v digital systems: the digital input pins (sck, sdi, convst and rd ) of the ltc1854/ltc1855/ltc1856 recognize 3v or 5v inputs. the ltc1854/ltc1855/ltc1856 have a dedicated output supply pin (ov dd ) that controls the output swings of the digital output pins (sdo, busy) and allows the part to interface to either 3v or 5v digital systems. the sdo output is twos complement. timing and control conversion start and data read are controlled by two digital inputs: convst and rd . to start a conversion and put the sample-and-hold into the hold mode bring convst high for at least 40ns. once initiated it cannot be restarted until the conversion is complete. converter status is indicated by the busy output, which goes low while the conversion is in progress. figures 6a and 6b show two different modes of opera - tion for the ltc1856. for the 12-bit ltc1854 and 14-bit ltc1855, the last four and two bits of the sdo will output zeros, respectively. in mode 1 (figure 6a), rd is tied low. the rising edge of convst starts the conversion. the data outputs are always enabled. the msb of the data output is available after the conversion. in mode 2 (figure 6b), convst and rd are tied together. the rising edge of the convst signal starts the conversion. data outputs are in three-state at this time. when the conversion is complete (busy goes high), convst and rd go low to enable the data output for the previous conversion. figure 5. ltc1856 histogram for 4096 conversions code ?4 ?3 0 count 200 600 800 1000 2 3 1800 185456 f05 400 ?2 ?1 0 1 4 1200 1400 1600 ltc1854/ltc1855/ltc1856 185456fa
17 applications information figure 6a. mode 1 for the ltc1856*. convst starts a conversion, data output is always enabled ( rd = 0) sgl/ diff 1 t 4 rd = 0 sck sdi sdo convst busy 2 3 4 5 6 7 8 15 16 odd/ sign select 1 select 0 x x nap sleep don?t care don?t care b14 b13 b12 b15 (msb) b11 b10 b9 b8 b1 b0 t acq t 7 t 6 t 2 t conv t 1 t 10 t 11 shift configuration word in sgl/ diff 1 2 3 4 5 6 7 8 15 16 odd/ sign select 1 select 0 x x nap sleep don?t care b14 b13 b12 b15 (msb) b11 b10 b9 b8 b1 b0 18545 f06a shift a/d result out and new configuration word in t 5 t 3 t 12 t 12 sgl/ diff 1 t 4 convst = rd sck sdi hi-z sdo busy 2 3 4 5 6 7 8 15 16 odd/ sign select 1 select 0 x x nap sleep don?t care don?t care b14 b13 b12 b15 (msb) b11 b10 b9 b8 t acq t 13 t 2 t conv hi-z t 10 t 11 shift configuration word in sgl/ diff 1 2 3 4 5 6 7 8 15 16 odd/ sign select 1 select 0 x x nap sleep don?t care b14 b13 b12 b15 (msb) b11 b10 b9 b8 hi-z shift a/d result out and new configuration word in t 5 t 3 t 9 t 8 t 7 t 6 185456 f06b b1 b0 b1 b0 sgl/ diff 1 t 4 rd sck sdi hi-z sdo busy convst 2 3 4 5 6 7 8 15 16 odd/ sign select 1 select 0 x x nap sleep don?t care don?t care b14 b13 b12 b15 (msb) b11 b10 b9 b8 t acq t 13 t 2 t 1 t conv hi-z t 10 t 11 shift configuration word in sgl/ diff 1 2 3 4 5 6 7 8 15 16 odd/ sign select 1 select 0 x x nap sleep don?t care b14 b13 b12 b15 (msb) b11 b10 b9 b8 hi-z shift a/d result out and new configuration word in t 5 t 3 t 9 t 8 t 7 t 6 185456 f07 b1 b0 b1 b0 figure 6b. mode 2 for the ltc1856*. convst and rd tied together. convst starts a conversion, data is read by rd figure 7. operating sequence for the ltc1856* *for the 12-bit ltc1854 and the ltc1855 the last four and two bits of the sdo will output zeros, respectively. ltc1854/ltc1855/ltc1856 1854565af
18 applications information serial data input (sdi) i nterface the ltc1854/ltc1855/ltc1856 communicate with micro - processors and other external circuitry via a synchronous, full duplex, 3- wire serial interface (see figure 7). the shift clock (sck) synchronizes the data transfer with each bit being transmitted on the falling sck edge and captured on the rising sck edge in both transmitting and receiving systems. the data is transmitted and received simultane - ously (full duplex). an 8-bit input word is shifted into the sdi input which confgures the ltc1854/ltc1855 /ltc1856 for the next conversion. simultaneously, the result of the previous conversion is output on the sdo line. at the end of the data exchange the requested conversion begins by ap - plying a rising edge on convst. after t conv , the conver - sion is complete and the results will be available on the next data transfer cycle. as shown below, the result of a conversion is delayed by one conversion from the input word requesting it. input d ata word the ltc1854/ltc1855/ltc1856 8-bit data word is clocked into the sdi input on the frst eight rising sck edges. fur - ther inputs on the sdi pin are then ignored until the next conversion. the eight bits of the input word are defned as follows: sdi sdo sdo word 0 sdi word 1 data transfer sdo word 2 sdi word 3 sdo word 1 sdi word 2 data transfer t conv a/d conversion t conv a/d conversion 185456 ai02 sgl/ diff select 1 select 0 don't care don't care mux address 185456 ai03 odd sign nap power down selection sleep table 1. multiplexer channel selection mux address differential channel selection mux address single-ended channel selection sgl/ diff odd sign select 1 0 0 1 2 3 4 5 6 7 sgl/ diff odd sign select 1 0 0 1 2 3 4 5 6 7 com 0 0 0 0 + C 1 0 0 0 + C 0 0 0 1 + C 1 0 0 1 + C 0 0 1 0 + C 1 0 1 0 + C 0 0 1 1 + C 1 0 1 1 + C 0 1 0 0 C + 1 1 0 0 + C 0 1 0 1 C + 1 1 0 1 + C 0 1 1 0 C + 1 1 1 0 + C 0 1 1 1 C + 1 1 1 1 + C figure 8. examples of multiplexer options on the ltc1854/ltc1855/ltc1856 0 1 2 3 4 5 6 7 channel com ( ? ) 8 single-ended + + + + + + + 0,1 channel 4 differential 2,3 4,5 6,7 + ( ? ) + + ( ? ) + ( ? ) + ( ? ) ? ( + ) ? ( + ) ? ( + ) ? ( + ) 4 5 6 7 channel com ( ? ) combinations of differential and single-ended + + + + + + 0,1 2,3 ? ? com (unused) changing the mux assignment ?on the fly? com ( ? ) 4,5 6,7 4,5 1st conversion 2nd conversion + ? + ? + ? + + 7 6 { { { { { { { { { 18545 f08 ltc1854/ltc1855/ltc1856 185456fa
19 applications information mux address the frst four bits of the input word assign the mux confguration for the requested conversion. for a given channel selection, the converter will measure the voltage between the two channels indicated by the + and C signs in the selected row of table 1. note that in differential mode (sgl/diff = 0) measurements are limited to four adjacent input pairs with either polarity. in single-ended mode, all input channels are measured with respect to com. both the + and C inputs are sampled simultaneously so common mode noise is rejected. bits 5 and 6 of the input words are dont care bits. p ower down selection (nap, sleep) the last two bits of the input word (nap and sleep) deter - mine the power shutdown mode of the ltc1854/ltc1855/ ltc1856. see table 2. nap mode is selected when nap = 1 and sleep = 0. the previous conversion result will be clocked out and a conversion will occur before entering the nap mode. the nap mode starts at the end of the conversion which is indicated by the rising edge of the busy signal. nap mode lasts until the falling edge of the 2nd sck (see figure 9). automatic nap will be achieved if nap = 1 is selected each time an input word is written to the adc. table 2. power down selection nap sleep power down mode 0 0 power on 1 0 nap x 1 sleep sleep mode will occur when sleep = 1 is selected, regardless of the selection of the nap input. the previ - ous conversion result can be clocked out and the sleep mode will start on the falling edge of the last (16th) sck. notice that the convst should stay either high or low in sleep mode (see figure 10). to wake up from the sleep mode, apply a rising edge on the convst signal and then apply sleep = 0 on the next sdi word and the part will wake up on the falling edge of the last (16th) sck (see figure 11). in sleep mode, all bias currents are shut down and only the power on reset circuit and leakage currents (about 10a) remain. sleep mode wake-up time is dependent on the value of the capacitor connected to the refcomp (pin 16). the wake-up time is typically 40ms with the recommended 10f capacitor connected on the refcomp pin. dynamic performance fft (fast fourier transform) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequencies outside the fundamental. figure 12 shows a typical ltc1856 fft plot which yields a sinad of 87db and thd of C 101db. ltc1854/ltc1855/ltc1856 1854565af
20 applications information figure 9. nap mode operation for the ltc1856* figure 10. sleep mode operation for the ltc1856* figure 11. wake up from sleep mode for the ltc1856* *for the 12-bit ltc1854 and the ltc1855 the last four and two bits of the sdo will output zeros, respectively. sgl/ diff 1 rd sck sdi hi-z sdo busy convst 2 3 4 5 6 7 8 15 16 odd/ sign select 1 select 0 x x nap = 1 sleep = 0 don?t care don?t care b14 b13 b12 b15 (msb) b11 b10 b9 b8 t conv hi-z nap t acq t acq shift configuration word in sgl/ diff 1 2 3 4 5 6 7 8 15 16 odd/ sign select 1 select 0 x x nap sleep don?t care b14 b13 b12 b15 msb b11 b10 b9 b8 hi-z shift a/d result out from previous conversion and new configuration word in 18545 f09 b1 b0 b1 b0 sgl/ diff 1 rd sck sdi sdo busy convst 2 3 4 5 6 7 8 15 16 odd/ sign select 1 select 0 x x nap sleep = 1 don?t care don?t care b14 b13 b12 b15 (msb) b11 b10 b9 b8 shift sleep configuration word in a/d result from previous conversion convst should stay either high or low in sleep mode t conv sleep 18545 f10 b1 b0 sgl/ diff 1 rd sck sdi sdo busy convst 2 3 4 5 6 7 8 15 16 odd/ sign select 1 select 0 x x nap sleep = 0 don?t care don?t care b14 b13 b12 b15 (msb) b11 b10 b9 b8 wake-up time ready t conv sleep shift wake-up configuration word in sgl/ diff 1 2 3 4 5 6 7 8 15 16 odd/ sign select 1 select 0 x x nap sleep don?t care b14 b13 b12 b15 (msb) b11 b10 b9 b8 a/d result not valid shift a/d result out and new configuration word in t conv 18545 f11 b1 b0 b1 b0 ltc1854/ltc1855/ltc1856 185456fa
21 applications information signal-to-noise and distortion r atio the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 12 shows a typical sinad of 87db with a 100khz sampling rate and a 1khz input. t otal harmonic d istortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: th d = 20l og v 2 2 + v 3 2 + v 4 2 ... + v n 2 v 1 where v 1 is the rms amplitude of the fundamental fre - quency and v 2 through v n are the amplitudes of the second through nth harmonics. board l ayout , power supplies and decoupling wire wrap boards are not recommended for high reso - lution or high speed a/d converters. to obtain the best performance from the ltc1854/ltc1855/ltc1856 , a printed circuit board is required. layout for the printed circuit board should ensure the digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. the analog input should be screened by agnd. in applications where the mux is connected to the adc, it is possible to get noise coupling into the adc from the trace connecting the muxout to the adc. therefore, reducing the length of the traces connecting the muxout pins (pins 10, 11) to the adc pins (pins 12, 13) can minimize the problem. the unused mux inputs should be grounded to prevent noise coupling into the inputs. figure 13 shows the power supply grounding that will help obtain the best performance from the 12-bit/14-bit/16-bit adcs. pay particular attention to the design of the analog and digital ground planes. the dgnd pin of the ltc1854/ figure 12. ltc1856 nonaveraged 4096 point fft plot frequency (khz) 0 15 25 50 185456 f12 5 10 20 30 40 45 35 magnitude (db) ?60 ?40 ?20 0 ?80 ?100 ?70 ?50 ?30 ?10 ?90 ?110 ?130 ?120 f sample = 100khz f in = 1khz sinad = 87db thd = ?101db ltc1854/ltc1855/ltc1856 1854565af
22 applications information ltc1855/ltc1856 can be tied to the analog ground plane. placing the bypass capacitor as close as possible to the power supply pins, the reference and reference buffer out - put is very important. low impedance common returns for these bypass capacitors are essential to low noise operation of the adc, and the foil width for these tracks should be as wide as possible. also, since any potential difference in grounds between the signal source and adc appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedance as much as possible. the digital output latches and the onboard sampling clock have been placed on the digital ground plane. the two ground planes are tied together at the adc through a wide, low inductance path. figure 13. power supply grounding practice 18545 f13 adc + ltc1854/ltc1855/ltc1856 digital system ov dd dgnd 24 21 adc ? 10 f dv dd 20 10 f av dd 19 agnd 14, 17, 18 10 f refcomp 16 10 f v ref 15 12 muxout + ltc1854/ ltc1855/ ltc1856 muxout ? 10 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 11 13 1 f analog ground plane digital ground plane + ? ltc1854/ltc1855/ltc1856 185456fa
23 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description g package 28-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640) g28 ssop 0204 0.09 ? 0.25 (.0035 ? .010) 0 ? 8 0.55 ? 0.95 (.022 ? .037) 5.00 ? 5.60** (.197 ? .221) 7.40 ? 8.20 (.291 ? .323) 12 34 5 6 7 89 10 11 12 14 13 9.90 ? 10.50* (.390 ? .413) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 2.0 (.079) max 0.05 (.002) min 0.65 (.0256) bsc 0.22 ? 0.38 (.009 ? .015) typ millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 ? 5.7 7.8 ? 8.2 recommended solder pad layout 1.25 0.12 ltc1854/ltc1855/ltc1856 1854565af
24 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0407 rev a ? printed in usa related parts typical application part number description comments sampling adcs ltc1418 14-bit, 200ksps, single 5v or 5v adc 15mw, serial/parallel i/o ltc1604 16-bit, 333ksps, 5v adc 90db sinad, 220mw power dissipation, pin compatible with ltc1608 ltc1605 16-bit, 100ksps, single 5v adc 10v inputs, 55mw, byte or parallel i/o, pin compatible with ltc1606 ltc1606 16-bit, 250ksps, single 5v adc 10v inputs, 75mw, byte or parallel i/o, pin compatible with ltc1605 ltc1608 16-bit, 500ksps, 5v adc 90db sinad, 270mw power dissipation, pin compatible with ltc1604 ltc1609 16-bit, 200ksps serial adc confgurable unipolar/bipolar input, up to 10v single 5v supply ltc1850/ltc1851 10-bit/12-bit, 8-channel, 1.25msps adc programmable mux and sequencer, parallel i/o ltc1859/ltc1858/ ltc1857 16-bit, 14-bit, 12-bit, 100ksps, softspan adcs software-selectable spans, pin compatible with ltc1864/ltc1865 16-bit, 1-/2-channel, 250ksps adc in msop single 5v supply, 850a with autoshutdown ltc1864l/ltc1865l 3v, 16-bit, 1-/2-channel, 150ksps adc in msop single 3v supply, 450a with autoshutdown ltc1856/ltc1855/ltc1854 dacs ltc1588/ltc1589 ltc1592 12-/14-/16-bit, serial, softspan i out dacs software-selectable spans, 1lsb inl/dnl ltc1595 16-bit serial multiplying i out dac in so-8 1lsb max inl/dnl, low glitch, dac8043 16-bit upgrade ltc1596 16-bit serial multiplying i out dac 1lsb max inl/dnl, low glitch, ad7543/dac8143 16-bit upgrade ltc1597 16-bit parallel, multiplying dac 1lsb max inl/dnl, low glitch, 4 quadrant resistors ltc1650 16-bit serial v out 5v dac low power, low glitch, 4-quadrant multiplication ltc2704-16/ ltc2704-14/ ltc2704-12 16-bit, 14-bit, 12-bit, serial, quad softspan v out dacs software-selectable spans, 2lsb inl, 1lsb inl, force/sense output 2.5v reference internal clock 1.6384x 4.096v 8k agnd1 control logic serial i/o input mux agnd3 agnd2 refcomp v ref adc ? muxout + muxout ? adc + dgnd av dd dv dd mux address data out convst 28 25 22 26 27 21 23 3v to 5v sdi busy sck rd ov dd sdo 18545 ta03 12-/14-/16-bit sampling adc + ? com 19 20 5v 5v 1 2 3 9 ch7 14 11 10 12 13 15 16 17 18 24 1f 0.1f ch1 single-ended or differential channel selection (see table 1) input range: 10v ? ? ? ch0 10f 0.1f 10f 8-bit serial data input 16 shift clock cycles 16-bit serial data out 10f 0.1f 10f 0.1f ltc1854/ltc1855/ltc1856 185456fa

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